(18, 9) Error correction code for double error correction and triple error detection

ABSTRACT

An (18, 9) error correction code that is simultaneously double error correcting and triple error detecting is disclosed. The code is defined by the following parity check matrix: 
                 β   1       3   ⁢               ⁢           ⁢       β   1     6     ⁢           ⁢       β   1     12     ⁢           ⁢           β   1     7     ⁢                       ⁢           ⁢       β   1     14     ⁢           ⁢       β   1     11     ⁢           ⁢       β   1     5     ⁢           ⁢       β   1     1     ⁢           ⁢       β   1     2     ⁢           ⁢       β   1     4     ⁢           ⁢       β   1     8     ⁢           ⁢                 ⁢   β     1     16     ⁢           ⁢       β   1     15     ⁢           ⁢       β   1     13     ⁢           ⁢       β   1     9     ⁢           ⁢               ⁢   0               ⁢   1       ⁢           ⁢       β   1     10     ⁢           ⁢     1     1   ,             
where β is a root of the polynomial x 17 −1 in the finite field of 256 elements. Logic circuitry for efficiently determining the locations of single and double errors as well as for detecting the presence of uncorrectable errors is also disclosed.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is related to the commonly owned, concurrently filedapplication of the same inventor, Ser. No. 10/744,833, entitled “Methodand Apparatus for Encoding Special Uncorrectable Errors in an ErrorCorrection Code”, now U.S. Pat. 7,171,591.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates, in general, to error correction codes forcomputers and data communications, and in particular to a special doubleerror correcting and triple error detecting code for computer memory.

2. Description of the Related Art

Error correction codes (ECCs) have long been used in computers as wellas data communications. Typically, such codes are constructed byappending r=n−k check symbols to k message symbols to form an n-symbolcode word, using a linear matrix transformation of the form:C=MG,where C=(c₀, c₁, . . . , c_(n−1)) is a 1×n row vector representing then-symbol code word, M=(m₀, m₁, . . . , m_(k−1)) is a 1×k row vectorrepresenting the k-symbol message or data word, and G is a k×n matrixknown as a generator matrix. (Alternatively, if C and M are assumed tobe column vectors, the transformation becomes C=G^(t)M, where G^(t) isthe transpose of G.) Although the symbols need not be bits, they areusually bits, and bits will be referred to in the discussion thatfollows. The code word C is either written to a storage medium ortransmitted over a communication channel. Both the storage medium andthe communication channel in the narrow sense may be regarded as“communication channels” in the broad sense.

On the decoding side, an n-bit word R is either retrieved from a storagemedium or received over a communication channel. This word R is the sumof the originally generated code word C and an n-bit error word E (whichmay be zero) representing any errors that may have occurred. Todetermine whether the received word accurately represents the originalcode word C, the received word R is used to generate a k-bit syndromevector using a matrix transformation of the form:S=RH^(t),where S is the syndrome vector and H^(t) is the transpose of an r×nmatrix H known as a parity check matrix. (Alternatively, if S is assumedto be a column vector, the transformation becomes S=HR^(t), where R^(t)is the transpose of R.)

The parity check matrix H is selected so that its row vectors lie in thenull space of those of the generator matrix G (i.e., GH^(t)=0), so thatfor an original code word C,CH^(t)=0.

Since R=C+E,S=(C+E)H ^(t) =CH ^(t) +EH ^(t)=0+EH ^(t) =EH ^(t).

In other words, the syndrome vector S is independent of the originalcode word C and a function only of the error word E. The decoder usesthe syndrome vector S to reconstruct the error word (following maximumlikelihood criteria), which is subtracted from the received word R toregenerate the code word C.

A code is the set of code words C generated from a given set of datawords M. (Even if two generator matrices differ, their code spaces maybe the same.) Codes are commonly classified by the number of symbols intheir data word M and code word C. Thus, an (n, k) code has a code wordof n symbols generated on a data word of k symbols.

The ability of a code to detect and correct errors depends on theso-called Hamming distance between different code words of the code. Ingeneral, the Hamming distance between two code words is the number ofsymbols in which the two code words differ. If the minimum Hammingdistance of a code is t+1, then the code can detect up to t errors,since if the code word has t or fewer errors, it will not have changedinto any other code word. Similarly, if the minimum Hamming distance ofa code is 2t+1, the code can correct up to t errors, since a receivedword having t or fewer errors will be within a Hamming distance of tsymbols on one and only one code word, and thus can be unambiguouslydecoded as that code word.

Furthermore, if the minimum Hamming distance of a code is 2t+2, the codecan correct up to t errors and also can detect t+1 errors, since areceived word having t+1 errors will not be within a Hamming distance oft symbols from any code word and thus will be detected as havinguncorrectable errors (UEs). From the foregoing, it will be apparent thatto correct 2 or fewer errors and simultaneously detect 3 errors, a codemust have a minimum Hamming distance of 6 symbols. Such codes arecommonly referred to as double error correcting and triple errordetecting (DEC-TED) codes. To give another example, codes with a minimumHamming distance of 4 symbols can correct a single error and detect upto 2 errors, and are known as single error correcting and double errordetecting (SEC-DED) codes.

Single error correcting and double error detecting (SEC-DED) codes havebeen widely used to protect computer memory subsystems from failures. Ascertain critical data such as storage protection keys in computersrequires a higher level of error protection, SEC-DED codes may not beadequate. In this case, a double error correcting, triple errordetecting (DEC-TED) code may be desired.

Error correction codes capable of correcting double errors and detectingtriple errors can be constructed based on the well-known BCH(Bose-Chaudhuri-Hocquenghem) theory (see W. Peterson and E. J. WeldonJr., Error-Correcting Codes, 1972, MIT Press). A primitive BCH DEC-TEDcode of length n=2^(m)−1 with 2m+1 check bits is obtained with a paritycheck matrix, each column vector k of which consists of 1, α^(k) andα^(3k), where α is a primitive element of the finite field of 2^(m)elements. Olderdissen describes a rapid decoding of the primitive BCHDEC-TED codes in U.S. Pat. No. 4,556,977. On the other hand, anon-primitive BCH DEC-TED code of length n=2^(m)+1 with 2m+1 check bitscan be obtained with a parity check matrix, each column vector k ofwhich consists of 1 and β^(k), where β is a primitive root of x^(n)−1 inthe finite field of 2^(2m) elements. A non-primitive BCH DEC-TED codeprovides two more data bits than a BCH DEC-TED code with the same numberof check bits. One drawback of the Olderdissen decoding scheme is thatit is not applicable to non-primitive BCH DEC-TED codes. In U.S. Pat.No. 4,117,458, Burghard and Coletti describe a decoding scheme based ona brute force table-look-up approach for a non-BCH code of length 17(=2⁴+1) with 8 data bits and 9 check bits. In addition, their errordetection scheme is limited to triple errors. The decoding table doesnot detect multiple errors beyond three that are theoreticallydetectable.

Recent ECC design for computer applications requires the ability todetect memory address errors as well as the ability to isolate componentfailures with invalid data indicators (see for examples U.S. Pat. No.6,457,154 for memory address error detection and U.S. Pat. No. 6,519,736for failure isolation of computer components with invalid dataindicators). For memory address error detection, extra data bits arerequired for encoding the parity of a memory address. A special datainvalid indicator, also known as a special UE (SPUE) indicator, isgenerated when the data sent out of a particular computer component tothe memory is known to be bad. As the special UEs come from differentcomputer components, it is desirable to be able to identify the sourcethat generates a particular special UE when the data associated with thespecial UE is fetched from the memory. To meet this requirement, extradata bits are also required for the encoding of the special UEs. In theprior art, a plurality of data bits are reserved for multiple specialUEs, which is inefficient in the usage of ECC data bits, especially whenthe number of available ECC data bits is limited.

SUMMARY OF THE INVENTION

In accordance with the present invention, there is provided a method andapparatus that correct all single and double errors, detect all tripleerrors, and detect a plurality of multiple errors for a DEC-TED code oflength n=18 with 9 data bits and 9 check bits. In general, one aspect ofthe present invention contemplates a method and apparatus for generatinga code word from a data word in accordance with an (18, 9) DEC-TED code.In accordance with this aspect of the invention, an 18-bit code word isgenerated from a 9-bit data word representing data to be encoded inaccordance with a linear code defined by the following parity checkmatrix:

${\underset{1}{\beta}}^{3\mspace{11mu}}\mspace{11mu}{\underset{1}{\beta}}^{6}\mspace{14mu}{\underset{1}{\beta}}^{12}\;{{\underset{1}{\beta}}^{7}\;}^{\;}\;{\underset{1}{\beta}}^{14}\mspace{11mu}{\underset{1}{\beta}}^{11}\mspace{11mu}{\underset{1}{\beta}}^{5}\mspace{14mu}{\underset{1}{\beta}}^{1}\mspace{14mu}{\underset{1}{\beta}}^{2}\mspace{14mu}{\underset{1}{\beta}}^{4}\mspace{14mu}{\underset{1}{\beta}}^{8}\mspace{11mu}{\underset{1}{\;\beta}}^{16}\mspace{11mu}{\underset{1}{\beta}}^{15}\mspace{14mu}{\underset{1}{\beta}}^{13}\mspace{14mu}{\underset{1}{\beta}}^{9}\mspace{14mu}\underset{\; 1}{\; 0}\mspace{25mu}{\underset{1}{\beta}}^{10}\mspace{11mu}\underset{1,}{1}$where β is a root of the polynomial x¹⁷−1 in the finite field of 256elements. In a preferred embodiment, β=α¹⁵, where α is a root of thebinary polynomial x⁸+x⁷+x⁶+x+1.

More particularly, this aspect of the invention contemplates an encoderthat generates an 18-bit code word C=(c₀, c₁, . . . , c₁₇) from a 9-bitdata word in accordance with a linear code in which bits c₀-c₆ andc₁₆-c₁₇ are data bits and bits c₇-c₁₅ are parity check bits satisfyingthe parity check equationCH₂ ^(t)=0,where H₂ ^(t) is the transpose of the parity check matrix H₂:

$\begin{matrix}0 & 1 & 0 & 1 & 1 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 1 \\1 & 0 & 1 & 0 & 1 & 1 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 \\0 & 1 & 0 & 1 & 0 & 1 & 1 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 \\0 & 0 & 1 & 0 & 1 & 0 & 1 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 1 & 1 \\1 & 0 & 0 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 1 & 1 \\1 & 1 & 0 & 0 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 1 \\0 & 1 & 1 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 1 & 1 \\1 & 0 & 1 & 1 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 1 \\1 & 1 & 1 & 1 & 1 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 1.\end{matrix}$

This aspect of the invention also contemplates a corresponding decoder.The decoder receives an 18-bit word R=(r₀, r₁, . . . , r₁₇) representingthe sum of the code word C and an 18-bit error word E=(e₀, e₁, . . . ,e₁₇). A syndrome generator of the decoder generates a 9-bit syndromevector S=(s₀, s₁, . . . s₈) from the received word R in accordance withthe matrix equationS=RH₁ ^(t),where H₁ ^(t) is the transpose of the parity check matrix H₁:

$\begin{matrix}0 & 0 & 1 & 1 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 1 & 1 & 1 & 0 & 0 & 0 & 1 \\0 & 0 & 0 & 0 & 1 & 1 & 1 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 \\1 & 1 & 1 & 0 & 0 & 1 & 0 & 1 & 1 & 0 & 1 & 1 & 1 & 1 & 0 & 0 & 0 & 0 \\0 & 0 & 1 & 0 & 1 & 0 & 0 & 1 & 0 & 1 & 0 & 1 & 0 & 0 & 1 & 0 & 0 & 0 \\1 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 1 & 1 & 0 & 0 & 0 \\0 & 1 & 1 & 0 & 0 & 0 & 1 & 1 & 0 & 0 & 0 & 1 & 1 & 1 & 0 & 0 & 1 & 0 \\0 & 0 & 1 & 1 & 0 & 0 & 1 & 1 & 1 & 0 & 1 & 1 & 1 & 0 & 1 & 0 & 1 & 0 \\1 & 1 & 1 & 1 & 0 & 1 & 0 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 \\0 & 0 & 1 & 0 & 1 & 0 & 1 & 1 & 0 & 1 & 1 & 1 & 0 & 1 & 0 & 1 & 1 & 0.\end{matrix}$

A syndrome decoder analyzes the received word R for errors using thesyndrome vector S. To decode the syndrome vector, the syndrome decoderuses various logic components as described below to determine thelocations of single and double errors, as well as to detect the presenceof uncorrectable (triple and higher-order) errors.

Additional features and advantages are realized through the techniquesof the present invention. Other embodiments and aspects of the inventionare described in detail herein and are considered a part of the claimedinvention. For a better understanding of the invention with advantagesand features, refer to the description and to the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter which is regarded as the invention is particularlypointed out and distinctly claimed in the claims at the conclusion ofthe specification. The foregoing and other objects, features, andadvantages of the invention are apparent from the following detaileddescription taken in conjunction with the accompanying drawings inwhich:

FIG. 1 illustrates one example of a computer system in which errorcorrection and error detection in accordance with the principles of thepresent invention may be utilized.

FIG. 2 illustrates one example of an error correction code format formemory address error detection and component failure isolation inaccordance with the present invention.

FIG. 3 a illustrates one example of a circuit used to generate aplurality of check bits associated with the data inputs in accordancewith the present invention

FIG. 3 b illustrates one example of a portion of the circuit of FIG. 3 aused to generate a single check bit.

FIG. 4 illustrates one example of an error correction and errordetection system for the received data in accordance to the presentinvention.

FIG. 5 a illustrates one example of a circuit used to generate aplurality of syndrome bits associated with the data inputs in accordancewith the present invention.

FIG. 5 b illustrates one example of a portion of the circuit of FIG. 5 aused to generate a single syndrome bit.

FIG. 6 illustrates one example of a circuit used to generate errorlocation indicators in accordance to the present invention.

FIG. 7 illustrates one example of a portion of the circuit in FIG. 6used to generate a preliminary single error location indicator.

FIG. 8 illustrates one example of a circuit used to generateuncorrectable error signal in accordance to the present invention.

The detailed description explains the preferred embodiments of theinvention, together with advantages and features, by way of example withreference to the drawings.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 is a block diagram representation of one embodiment of a computersystem 100 utilizing the error correction code of the present invention.In the embodiment shown, computer system 100 includes a memory 110connected to a main storage controller (MSC) 120 via a data bus 115, acache 130 connected to MSC 120 via an MSC-cache interface 116, and aplurality of central processing units (CPUs) 140 connected to cache 130via data buses 117. MSC-cache interface 116 and data buses 117 are usedto transfer data between MSC 120 and cache 130 and between cache 130 andCPUs 140, respectively. Transfer of data between memory 110 and MSC 120,on the other hand, occurs via data bus 115. Thus, data bus 115facilitates the reading of data from memory 110 as well as the writingof data to memory 110 by MSC120.

A subset of the data area in cache 130 is a storage protection key area(SP KEY) 118, which contains storage protection keys generated to assuredata integrity in the cache. In accordance with the present invention,storage protection keys from key area 118 are constantly updated andstored in memory 110, as is all data from the cache 130. However,because storage protection keys are considered critical data thatrequire a higher level of reliability, a more potent ECC is selected forerror protection of these keys. In particular, a DEC-TED code is used tocorrect all single or double errors, detect all triple errors and alsodetect a plurality of multiple errors in an encoded ECC word, asdescribed further below.

In the embodiment shown, a storage protection key consists of 7 bits. Inaddition, one data bit is used for encoding of the memory addressparity, while another data bit is used for encoding of two specialuncorrectable errors (UEs). Thus, a total of 9 data bits are requiredfor the ECC. This leads to an (18, 9) DEC-TED code that consists of 18bits in a code word with 9 data bits and 9 check bits. Note that aspecial UE (SPUE) is a data validity indicator generated when the datasent out of a particular computer component to the memory is known to bebad. As the special UEs come from different computer components, it isdesirable to be able to identify the source that generates a particularspecial UE when the data associated with the special UE is fetched fromthe memory.

FIG. 2 shows the ECC word structure according to one embodiment of theinvention. The first 7 bits (bits 0-6) contain the original storageprotection key data. The next 9 bits (bits 7-15) are check bitsgenerated from bits 0-6 and bits 16-17 according to the ECC equations tobe described shortly. Bit 16 (SPUE) is assigned for special UEs.Finally, an address parity bit AP (bit 17) is assigned for the parity ofthe memory address. Only the first 16 bits (bits 0-15) are stored inmemory 110 (FIG. 1). Though bits 16 and 17 are used in the generation ofcheck bits, they are not stored in memory 110. In reading data frommemory 110, the address parity bit AP is made available to the ECCdecoder, while the value of the SPUE bit is assumed to be zero. If,however, the syndrome decoder to be described detects an error at bitlocation 16 (assuming a bit value of zero at that location), then itdetermines that the SPUE bit is one and that bits 0-6 encode a SPUE.Thus, even though the SPUE bit is not stored as such, it is effectivelyencoded in the 16 bits of the code word that are stored in memory 110through its use in generating the check bits 7-15.

The value of the SPUE bit is 0 for a valid storage protection key. A keyis marked invalid when the data received from other components of thecomputer system is known to be bad. In such case, the value of SPUE isset to 1. Conventionally, plural data bits are used in order todifferentiate the sources of the bad data. In the present invention, bycontrast, only one data bit (bit 16) is used. To identify the source ofthe bad data, the associated key data bits (bits 0-6) are modified sothat different sources of bad data are represented by different patternof bits 0-6. For example, to differentiate bad data from cache 130 frombad data from MSC 120 (FIG. 1), two 7-bit patterns (0000000) and(1111111) can be assigned to bits 0-6 (FIG. 2). As an illustration,(0000000) may be assigned to be the pattern of bits 0-6 and SPUE bit 16set to 1 if the bad data originated from cache 130, while (1111111) maybe assigned to be the pattern of bits 0-6 and SPUE bit 16 set to 1 ifthe bad data originated from MSC 120. Other possible pattern pairs are(1010101, 0010100) and (0001111, 1110000).

Now suppose that one of the SPUE patterns is stored in memory 110 andthen retrieved. In accordance with the ECC decoding method to bedescribed, if there is no error in the memory, a unique error syndrome010001111 is generated and the ECC decoding flags bit 16 to be in error.This indicates that the data received is associated with a SPUE. Thepattern in bits 0-6 is then used to identify the original source of baddata. If there is an error in the memory in which the SPUE data resided,the ECC decoding would detect the presence of two errors, one of whichis a memory error and the other of which is bit 16. The error syndromedepends on the location of the memory error. In any case, the syndromeis a double error syndrome and will be decoded as such because the codeis capable of correcting double errors. Again, upon the error detectionof bit 16 the source of the bad data can be isolated.

An ECC can be specified by a set of equations that all encoded ECC wordshave to satisfy. Let C=(c₀, c₁, c₂, . . . , c₁₇) be a 1×18 row vectordefining a code word. The (17, 8) DEC-TED code described in U.S. Pat.No. 4,117,458 is a non-primitive BCH code that can be lengthened by onebit to yield a (18, 9) DEC-TED code. Including the all-one 18-bit vectorin the code space does this. The (18, 9) DEC-TED code of the presentinvention is defined by the following two equations:c ₀β³ +c ₁β⁶ +c ₂β¹² +c ₃β⁷ +c ₄β¹⁴ +c ₅β¹¹ +c ₆β⁵ +c ₇ β.+c ₈β² +c ₉β⁴+c ₁₀β⁸ +c ₁₁β¹⁶ +c ₁₂β¹⁵ +c ₁₃β¹³ +c ₁₄β⁹ +c ₁₅0+c ₁₆β¹⁰ +c ₁₇β⁰=0c ₀ +c ₁ +c ₂ +c ₃+c₄ +c ₅ +c ₆ +c ₇ +c ₈ +c ₉ +c ₁₀ +c ₁₁ +c ₁₂ +c ₁₃+c ₁₄ +c ₁₅ +c ₁₆ +c ₁₇=0.

The additions in the above equations are performed according to therules of the finite field of 256 elements. The first equation specifiesthe (17, 9) code listed on page 494 of the above-identified work ofPeterson et al. and guarantees that the number of nonzero terms is atleast 5 for a nonzero code word. The second equation says that thenumber of nonzero terms in a code word is even, since each c; is binary.As explained on page 119 of the same work, combining both equationsmeans that the number of nonzero terms of a nonzero code word is atleast 6, i.e., the Hamming distance of the code is 6. Note that thefirst equation involves all 17 unique powers of β. In this firstequation, the terms of the powers of β are not arranged in a sequentialorder. However, the ordering is not critical; any ordering works.

The symbol β in the above equations is a primitive root of x¹⁷−1 in thefinite field of 256 elements. Specifically, β=α¹⁵, where α is a root ofthe binary primitive polynomial x⁸+x⁷+x⁶+x+1. The same code space can bedefined using an irreducible polynomial. However, in practicalapplication, the particular choice presented here has been empiricallyshown to lead to a simpler implementation. Notice that α is primitiveelement of the finite field of 256 elements, and β is also an element ofthe same finite field.

The above equations that define the ECC can be expressed in matrix formas CH^(t)=0, where H^(t) denotes the transpose of the matrix H:

${\underset{1}{\beta}}^{3\mspace{11mu}}\mspace{11mu}{\underset{1}{\beta}}^{6}\mspace{14mu}{\underset{1}{\beta}}^{12}\;{{\underset{1}{\beta}}^{7}\;}^{\;}\;{\underset{1}{\beta}}^{14}\mspace{11mu}{\underset{1}{\beta}}^{11}\mspace{11mu}{\underset{1}{\beta}}^{5}\mspace{14mu}{\underset{1}{\beta}}^{1}\mspace{14mu}{\underset{1}{\beta}}^{2}\mspace{14mu}{\underset{1}{\beta}}^{4}\mspace{14mu}{\underset{1}{\beta}}^{8}\mspace{11mu}{\underset{1}{\;\beta}}^{16}\mspace{11mu}{\underset{1}{\beta}}^{15}\mspace{14mu}{\underset{1}{\beta}}^{13}\mspace{14mu}{\underset{1}{\beta}}^{9}\mspace{14mu}\underset{\; 1}{\; 0}\mspace{25mu}{\underset{1}{\beta}}^{10}\mspace{11mu}\underset{1.}{1}$

It can be shown that the code defined by matrix H is a DEC-TED code. Inaddition, the columns of the matrix can be permuted in any order withoutreducing the capability of error correction and error detection.

The finite field elements in matrix H can be expressed in binary vectorsto facilitate implementation using digital circuitry. Specifically,matrix H can be transformed into a 9×18 binary matrix H₁:

$\begin{matrix}\begin{matrix}0 & 0 & 1 & 1 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 1 & 1 & 1 & 0 & 0 & 0 & 1 \\0 & 0 & 0 & 0 & 1 & 1 & 1 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 \\1 & 1 & 1 & 0 & 0 & 1 & 0 & 1 & 1 & 0 & 1 & 1 & 1 & 1 & 0 & 0 & 0 & 0 \\0 & 0 & 1 & 0 & 1 & 0 & 0 & 1 & 0 & 1 & 0 & 1 & 0 & 0 & 1 & 0 & 0 & 0 \\1 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 1 & 1 & 0 & 0 & 0 \\0 & 1 & 1 & 0 & 0 & 0 & 1 & 1 & 0 & 0 & 0 & 1 & 1 & 1 & 0 & 0 & 1 & 0 \\0 & 0 & 1 & 1 & 0 & 0 & 1 & 1 & 1 & 0 & 1 & 1 & 1 & 0 & 1 & 0 & 1 & 0 \\1 & 1 & 1 & 1 & 0 & 1 & 0 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 \\0 & 0 & 1 & 0 & 1 & 0 & 1 & 1 & 0 & 1 & 1 & 1 & 0 & 1 & 0 & 1 & 1 & 0.\end{matrix} & (1)\end{matrix}$

The derivation of H₁ from H may be briefly explained. Assume, as before,that α is a root of x⁸+x⁷+x⁶+x+1 and β=α¹⁵. Then a power of β, can beexpressed as a polynomial in terms of powers of α. The coefficients ofthe polynomial are a binary 8-bit vector listed in the first 8 bits of acolumn vector in the H₁ matrix above. Now, the field element 1corresponds to the 8-bit vector 10000000. The second row of the H matrixabove is an all ones vector. It is translated into a 8-row binary matrixwith the first row being all ones and the rest of the rows being allzeros, which can be discarded. This explains how the original matrix istranslated into a 9-row binary matrix. However, the last row of the H₁matrix above is not all ones. The all ones row vector has been replacedby the sum (exclusive OR) of all 9 row vectors so that each columncontains an odd number of ones. If you add all 9 row vectors together,you obtain an all ones vector. There is no difference in the spacesdefined by H and H₁.

In reading data from the memory, matrix H₁ is used to check if an 18-bitreceived vector R is a legitimate code word by calculating the syndromeS by the formula S=RH₁ ^(t), where H₁ ^(t) is the transpose of thevector H₁. Vector R is assumed to be a code word if the syndrome S is anall zeros vector. If S is not an all zeros vector, the ECC decoder to bedescribed is used to determine if R contains one or two errors and alsoto determine the associated error positions. The decoder is also used todetermine if R contains detectable uncorrectable errors (UEs), whichinclude the set of all triple errors and some higher-order errors thatare also detectable, though not correctable. Let S=(s₀, s₁, . . . , s₈).The received bits marked with the ones in row i of matrix H₁ are summedtogether using exclusive OR (XOR) operations to obtain the value ofs_(i). Specifically, the syndrome bits are obtained by the followingformulas.s₀=XOR of input bits 2, 3, 4, 6, 11, 12, 13, 17s₁=XOR of bits 4, 5, 6, 7, 9, 16s₂=XOR of bits 0, 1, 2, 5, 7, 8, 10, 11, 12, 13s₃=XOR of bits 2, 4, 7, 9, 11, 14s₄=XOR of bits 0, 4, 11, 12, 13, 14s₅=XOR of bits 1, 2, 6, 7, 11, 12, 13, 16s₆=XOR of bits 2, 3, 6, 7, 8, 10, 11, 12, 14, 16s₇=XOR of bits 0, 1, 2, 3, 5, 7, 8, 16s₈=XOR of bits 2, 4, 6, 7, 9, 10, 11, 13, 15, 16.  (2)

Let us label the columns of matrix H₁ as columns 0, 1, . . . , 17. Forthe generation of check bits, H₁ is multiplied by the inverse of thematrix formed by its columns 7-15 to obtain the matrix H₂:

$\begin{matrix}\begin{matrix}0 & 1 & 0 & 1 & 1 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 1 \\1 & 0 & 1 & 0 & 1 & 1 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 \\0 & 1 & 0 & 1 & 0 & 1 & 1 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 \\0 & 0 & 1 & 0 & 1 & 0 & 1 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 1 & 1 \\1 & 0 & 0 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 1 & 1 \\1 & 1 & 0 & 0 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 1 \\0 & 1 & 1 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 1 & 1 \\1 & 0 & 1 & 1 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 1 \\1 & 1 & 1 & 1 & 1 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 1.\end{matrix} & (3)\end{matrix}$

Notice that columns 7-15 of H₂ form a 9×9 identity matrix. The value ofeach check bit is calculated from a row vector of H₂. Let C=(c₀, c₁, c₂,. . . , c₁₇) be a code word. Since for a properly formed code word C,CH₂ ^(t)=0, each row of H₂ is in effect a statement that the XOR sum ofa given check bit and the data bits indicated by the ones in the row iszero or, equivalently, that the check bit is the XOR sum of those databits. Given the values of bits 0-6 and bits 16-17 in the code word, thevalues of bits 7-15 are calculated from the following formulas(corresponding to the rows of H₂) in terms of exclusive OR operations:c₇=XOR of bits 1, 3, 4, 16, 17c₈=XOR of bits 0, 2, 4, 5, 17c₉=XOR of bits 1, 3, 5, 6, 17c₁₀=XOR of bits 2, 4, 6, 16, 17c₁₁=XOR of bits 0, 3, 5, 16, 17c₁₂=XOR of bits 0, 1, 4, 6, 17c₁₃=XOR of bits 1, 2, 5, 16, 17c₁₄=XOR of bits 0, 2, 3, 6, 17c₁₅=XOR of bits 0, 1, 2, 3, 4, 5, 6, 16, 17.  (4)

To calculate the check bits above, it is not necessary to obtain anexplicit value for a generator matrix G. However, it can readily beshown (see, e.g., chapter 3 of the Peterson et al. reference identifiedabove) that matrix H₂ is a parity check matrix for a code having thefollowing as a generator matrix G:

$\begin{matrix}1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 1 & 1 & 0 & 1 & 1 & 0 & 0 \\0 & 1 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 1 & 0 & 0 & 1 & 1 & 0 & 1 & 0 & 0 \\0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 1 & 0 & 0 & 1 & 1 & 1 & 0 & 0 \\0 & 0 & 0 & 1 & 0 & 0 & 0 & 1 & 0 & 1 & 0 & 1 & 0 & 0 & 1 & 1 & 0 & 0 \\0 & 0 & 0 & 0 & 1 & 0 & 0 & 1 & 1 & 0 & 1 & 0 & 1 & 0 & 0 & 1 & 0 & 0 \\0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 1 & 1 & 0 & 1 & 0 & 1 & 0 & 1 & 0 & 0 \\0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 1 & 1 & 0 & 1 & 0 & 1 & 1 & 0 & 0 \\0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 1 & 1 & 0 & 1 & 0 & 1 & 1 & 0 \\0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 0 & 1\end{matrix}$

Columns 0-6 and 16-17 of G form an identity matrix, while columns 7-15form the transpose of the matrix formed by columns 0-6 and 7-15 of H₂.Since columns 0-6 and 16-17 of G form an identity matrix, bits 0-6 and16-17 of a code word C are simply the corresponding bits of the originaldata word (hence their label as information bits). Check bits 7-15 mayalternatively be calculated using columns 7-15 of generator matrix G(with the bits SPUE and AP being regarded as bits 7 and 8 of theoriginal data word). Since columns 7-15 of G are simply the transpose ofthe matrix formed by columns 0-6 and 7-15 of H₂, the resulting XORoperations are identical to the operations (4) set forth above.

As described earlier, the syndrome S of a received vector R is used inthe decoding to determine the nature of the errors if S is not zero. Letsp be the parity of the syndrome bits. That is, sp is the XOR of all 9syndrome bits. Since each column of the parity check matrix H₁ containsan odd number of ones, an error in any one bit of the received vector Rwill invert (i.e., flip) an odd number of syndrome bits, therebyinverting their XOR sum sp. Accordingly, sp=0 if there is an even numberof errors in R, and sp=1 if there is an odd number of errors in R. Thus,the decoder can easily determine whether the number of errors is even orodd. If the number of errors is odd, the decoder assumes that there isone error and it goes on to determine the single error position. Onother hand, if the number of errors is even, the decoder assumes thatthere are two errors and it goes on to determine the locations of twoerrors.

Single error position is relatively easy to determine. If the first 8bits of column i of H₁ are identical to the first 8 syndrome bits, thenbit i is identified as the single error location.

Double error positions are not trivial to identify. An equation with theerror locations as unknown variables has to be derived and solved. Letx₁ and x₂ be two unknown variables representing the error locations interms of the finite field of 256 elements. Each variable is either apower of β or 0. Let S₁ be the first 8 bits of the syndrome and considerS₁ as an element of the finite field. From the first row of matrix H andthe equation HC^(t)=0, the syndrome is related to the error locations x₁and x₂ by the equation S₁=x₁+x₂. In addition, it can be shown that errorlocations x₁ and x₂ are roots of x¹⁸−x. That is, x₁ ¹⁸−x₁=0 and x₂¹⁸−x₂=0. Combining all these relations, it can be shown that x₁ and x₂are solutions to the following equation with x as the unknown variable.S ₁ ¹⁷ =x ¹⁶ S ₁ +x S ₁ ¹⁶  (5)

The values of x₁ and x₂ are obtained by solving equation (5) for x.Special attention is required in the case that one of the two errors islocated at bit 15, which has a 0 as the field element in matrix H. Inthis case, equation (5) is not used. Instead, S₁ is treated as a singleerror syndrome, and the second error location is identified by matchingS₁ with the column vectors of the first 8 rows of H₁.

Let E_(i) be the error indicator for bit i with the property thatE_(i)=0 if bit i is not in error and E_(i)=1 if bit i is in error. Thedecoder is used to generate the values of E_(i) for all bit positions.One decoding algorithm (Algorithm A) is described below:

-   -   1. If all 9-syndrome bits are zero, there is no error and the        received data is not altered. Exit the algorithm.    -   2. Set E₁₅=1 if (a) S₁=0 and sp=1;or (b) S₁ ¹⁷=1 and sp=0, where        S₁ is the first 8 bits of the syndrome S and is considered a        field element, and sp is the exclusive OR sum of all syndrome        bits.    -   3. For 0≦i≦17 and i≠15: set E_(i)=1 if (a) S₁=column i of the        first 8 rows of H₁ and S₁ ¹⁷ =1; or (b) the field element x_(i)        of column i of the first 8 rows of H₁ satisfies x_(i)        ¹⁶S+x_(i)S₁ ¹⁶=S₁ ¹⁷, S₁ ¹⁷≠1, S₁≠0, and sp=0.    -   4. Set UE=1 if (a) S₁ ¹⁷≠1, S₁≠0 and sp=1; or (b) S₁ ¹⁷≠1, sp=0        and there is no solution to x_(i) ¹⁶S₁+x_(i)S₁ ¹⁶=S₁ ¹⁷.

If the value of E₁₆ obtained from Algorithm A is 1, the received data Ris a SPUE. In this case, the data bits in bits 0-6 after errorcorrection are used to determine the nature of the SPUE, which resultsin failure isolation.

The components of the 8-bit vector S₁ ¹⁷ are not independent. It can beshown that bits 0, 1, 2, and 4 are linearly independent and that theremaining 4 bits can be derived from these independent bits. (Moregenerally, the exact positions of the independent bits depend on thepolynomial defining the field, but the number of independent bits isalways 4.) Thus, S₁ ¹⁷ can be replaced by S₁ ¹⁷ (0, 1, 2, 4), whichrepresents bits 0, 1, 2, 4 of S₁ ¹⁷ in Algorithm A. These 4 bits can beobtained from the following formulas:S₁ ¹⁷(0)=XOR of S(0), S(2), S(3), S(6), S(0)S(1), S(0)S(5), S(0)S(7),S(1)S(2), S(1)S(6), S(1)S(7), S(2)S(4), S(2)S(6), S(3)S(6), S(3)S(7),S(4)S(5), S(4)S(7)S₁ ¹⁷(1)=XOR of S(1), S(3), S(4), S(7), S(0)S(2), S(0)S(3), S(0)S(6),S(1)S(2), S(1)S(6), S(2)S(3), S(2)S(7), S(3)S(5), S(3)S(7), S(4)S(7),S(5)S(6)S₁ ¹⁷(2)=XOR of S(1), S(2), S(5), S(0)S(1), S(0)S(5), S(0)S(6),S(0)S(7), S(1)S(3), S(1)S(5), S(2)S(5), S(2)S(6), S(3)S(4), S(3)S(6),S(3)S(7), S(4)S(7), S(5)S(7)S₁ ¹⁷(4)=XOR of S(1), S(2), S(3), S(4), S(6), S(0)S(1), S(0)S(2),S(0)S(4), S(0)S(5), S(1)S(2), S(1)S(4), S(1)S(5), S(1)S(6), S(2)S(3),S(2)S(4), S(2)S(5), S(2)S(7), S(4)S(5), S(4)S(6), S(5)S(7),S(6)S(7)  (6)

In equation (6), S(i) denotes bit i of the syndrome S and S(i)S(j) isthe product of S(i) and S(j).

One embodiment of the hardware implementation of the ECC encoding anddecoding is described next.

FIG. 3 a shows an encoder 200 for ECC encoding. Input data (DATA IN) 210consists of the 7-bit storage protection key data to be encoded. Twoother inputs to the encoder 200 are the special uncorrectable error bitSPUE and the memory address parity bit AP shown in FIG. 2. The key data210 is sent to a modification circuit (DATA MODIFIED) 240 that has SPUEas the other input. If SPUE is 0, the key data 210 is not modified. Onthe other hand, if SPUE is 1, circuit 240 modifies the key data 210according to the pre-defined SPUE data patterns as described above. Theoutput of circuit 240 appears as output data (DATA OUT) 220. It is alsosent to an check symbol generator 250 comprising an XOR gate arraycontaining XOR circuits 260-268 (XOR0-XOR8). XOR circuits 260-268generate check bits according to equation (4). Thus, FIG. 3 billustrates the generation of check bit 0 (bit 7 of the encoded word)using XOR circuit 260 according to equation (4).

The output of the XOR gate array 250 appears as check bits 230. Bits0-15 of the encoded ECC word (bits 0-17) consist of the output data 220(bits 0-6) and check bits 230 (bits 7-15). As noted above, bits 0-15 ofthe code word are stored in memory 110, while bit 16 (SPUE) is assumedto be zero and bit 17 (AP) of the code word is independently regeneratedwhen bits 0-15 of the code word are later read out of the memory 110.

FIG. 4 is a block diagram of a decoder 300 for data read from memory110. The received 16-bit word is stored in an input register (DATA IN)400, of which the first 7 bits represent the data bits and the last 9bits represent the check bits. The entire 16-bit word in input register400 is sent to a syndrome generator (SYNDROME GEN) 500 that has theaddress parity bit AP as another input. (Since SPUE information is notavailable, it is assumed to be zero.) Syndrome generator 500 generatesas an output all 9 syndrome bits, which are sent to a syndrome decoder(SYNDROME DECODE) 600 for the generation of error location indicatorsE_(i) and a one-bit uncorrectable error indicator UE. The errorindicators E_(i) for 0≦i≦6 from syndrome decoder 600 and the 7 data bitsfrom input register 400 are XORed bitwise by a data correction circuit700 to produce corrected output data.

FIG. 5 a shows the syndrome generator 500. The inputs are the 16received bits—7 data bits (0-6) and 9 check bits (7-15)—stored in inputregister 400 and the AP bit (17). The 9-bit output is stored in asyndrome register (SYNDROME REG) 520. The 9 syndrome bits are generatedby XOR blocks 530-538, each of which contains logic for performing anXOR operation specified in equation (2).

FIG. 5 b shows, by way of illustration, the input bits (2-4, 6, 11-13,AP=17) for XOR block 530, which generates syndrome bit 0. Notice thatbit 17 appears only once in equation (2); only XOR block 530 takes AP asan input.

FIG. 6 shows the syndrome decoder 600, which generates the errorindicator E₁₅ as well as error indicators E_(i) for i≠15 in accordancewith steps 2 and 3, respectively, of Algorithm A. Although not shown inFIG. 6, syndrome decoder 600 also contains uncorrectable error (UE)detection logic 660 (FIG. 8) for generating an uncorrectable error (UE)signal indicating the presence of an uncorrectable error. In thisfigure, for i≠15, E₁, i=1 indicates that S₁=column i of the first 8 rowsof H₁, while E_(2,i)=1 indicates that the field element x_(i) of columni of the first 8 rows of H₁ satisfies the equation x_(i) ¹⁶S+x_(i) S₁¹⁶=S₁ ¹⁷. Each AND block 632-636 outputs the logical AND of its inputs,while each OR block 641-643 outputs the logical OR of its inputs andeach inverter block 651-653 (denoted by a triangle) outputs the logicalinverse of its input. A syndrome parity bit sp is generated by an XORcircuit 602 that outputs the exclusive OR of all 9 syndrome bits, storedin a syndrome register (SYNDROME S) 601. Also, a vector S₁ (603) isextracted as the first 8 bits of the syndrome vector S.

Single error location logic 610 performs the function of matching inputS₁ (603) with the column vectors of the first 8 rows of H₁ of equation(1). The output bits are single error indicators E_(1,i). FIG. 7illustrates by way of example the circuit for generating the singleerror indicator E_(1,0). (The triangles in the figure denote logicalinverters.) The circuit matches an 8-bit input (0-7) with column 0 ofthe first 8 rows of H₁ to produce an output E_(1,0) of 1 if and only ifeach input bit matches the corresponding bit of that column of H₁.

Logic 630 in FIG. 6 generates as the output S₁ ¹⁷ (0, 1, 2, 4) for bits0, 1, 2, and 4 of S₁ ¹⁷ according to equation (6). This generated outputis used to represent S₁ ¹⁷.

Double error location logic 620 generates the double error indicatorsE_(2,i). The inputs to logic 620 include S₁ ¹⁷ (0, 1, 2, 4) from logic630 and S₁ (603). The outputs E_(2,i) of logic 620 are generated asfollows. Logic 620 first generates a set of comparison bits Fi fromsyndrome bits 0-7 according to the following formulas:F1=syndrome bit 7,F3=XOR of syndrome bits 6, 7,F4=syndrome bit 5,F14=XOR of syndrome bits 4, 5, 6,F18=XOR of syndrome bits 3, 6,F20=XOR of syndrome bits 3, 5,F21=XOR of syndrome bits 3, 5, 7,F23=XOR of syndrome bits 3, 5, 6, 7,F26=XOR of syndrome bits 3, 4, 6,F29=XOR of syndrome bits 3, 4, 5, 7,F30=XOR of syndrome bits 3, 4, 5, 6,F40=XOR of syndrome bits 2, 4,F42=XOR of syndrome bits 2, 4, 6,F44=XOR of syndrome bits 2, 4, 5,F45=XOR of syndrome bits 2, 4, 5, 7,F49=XOR of syndrome bits 2, 3, 7,F50=XOR of syndrome bits 2, 3, 6,F52=XOR of syndrome bits 2, 3, 5,F58=XOR of syndrome bits 2, 3, 4, 6,F69=XOR of syndrome bits 1, 5, 7,F71=XOR of syndrome bits 1, 5, 6, 7,F74=XOR of syndrome bits 1, 4, 6,F85=XOR of syndrome bits 1, 3, 5, 7,F86=XOR of syndrome bits 1, 3, 5, 6,F89=XOR of syndrome bits 1, 3, 4, 7,F96=XOR of syndrome bits 1, 2,F98=XOR of syndrome bits 1, 2, 6,F107=XOR of syndrome bits 1, 2, 4, 6, 7,F108=XOR of syndrome bits 1, 2, 4, 5,F123=XOR of syndrome bits 1, 2, 3, 4, 6, 7,F130=XOR of syndrome bits 0, 6,F131=XOR of syndrome bits 0, 6, 7,F135=XOR of syndrome bits 0, 5, 6, 7,F137=XOR of syndrome bits 0, 4, 7,F139=XOR of syndrome bits 0, 4, 6, 7,F142=XOR of syndrome bits 0, 4, 5, 6,F143=XOR of syndrome bits 0, 4, 5, 6, 7,F145=XOR of syndrome bits 0, 3, 7,F148=XOR of syndrome bits 0, 3, 5,F160=XOR of syndrome bits 0, 2,F162=XOR of syndrome bits 0, 2, 6,F168=XOR of syndrome bits 0, 2, 4,F177=XOR of syndrome bits 0, 2, 3, 7,F178=XOR of syndrome bits 0, 2, 3, 6,F180=XOR of syndrome bits 0, 2, 3, 5,F182=XOR of syndrome bits 0, 2, 3, 5, 6,F183=XOR of syndrome bits 0, 2, 3, 5, 6, 7,F184=XOR of syndrome bits 0, 2, 3, 4,F190=XOR of syndrome bits 0, 2, 3, 4, 5, 6,F192=XOR of syndrome bits 0, 1,F198=XOR of syndrome bits 0, 1, 5, 6,F199=XOR of syndrome bits 0, 1, 5, 6, 7,F202=XOR of syndrome bits 0, 1, 4, 6,F203=XOR of syndrome bits 0, 1, 4, 6, 7,F204=XOR of syndrome bits 0, 1, 4, 5,F206=XOR of syndrome bits 0, 1, 4, 5, 6,F209=XOR of syndrome bits 0, 1, 3, 7,F210=XOR of syndrome bits 0, 1, 3, 6,F213=XOR of syndrome bits 0, 1, 3, 5, 7,F215=XOR of syndrome bits 0, 1, 3, 5, 6, 7,F223=XOR of syndrome bits 0, 1, 3, 4, 5, 6, 7,F226=XOR of syndrome bits 0, 1, 2, 6,F232=XOR of syndrome bits 0, 1, 2, 4,F234=XOR of syndrome bits 0, 1, 2, 4, 6,F237=XOR of syndrome bits 0, 1, 2, 4, 5, 7,F240=XOR of syndrome bits 0, 1, 2, 3,F247=XOR of syndrome bits 0, 1, 2, 3, 5, 6, 7,F251=XOR of syndrome bits 0, 1, 2, 3, 4, 6, 7,

Note that the syndrome bits participating in the XOR operations for Ficorrespond to the binary representation of the integer i. For example,the binary representation of 226 is 11100010, and F226 is the XOR ofsyndrome bits 0, 1, 2, 6.

Logic 620 then generates a set of error values E_(2,j) for 0≦j≦17 andj≠15 by comparing the bits of S₁ ¹⁷(0, 1, 2, 4) with selected bits Fi,as indicated below. Each generated error value E_(2,j) is one if thebits all match and is otherwise zero. More particularly:E _(2,0)=1 if S ₁ ¹⁷(0, 1, 2, 4)=(F183, F232, F139, F29)E _(2,1)=1 if S ₁ ¹⁷(0, 1, 2, 4)=(F26, F251, F123, F18)E _(2,2)=1 if S ₁ ¹⁷(0, 1, 2, 4)=(F44, F168, F199, F23)E _(2,3)=1 if S ₁ ¹⁷(0, 1, 2, 4)=(F237, F206, F107, F3)E _(2,4)=1 if S ₁ ¹⁷(0, 1, 2, 4)=(F192, F180, F137, F4)E _(2,5)=1 if S ₁ ¹⁷(0, 1, 2, 4)=(F49, F203, F14, F85)E _(2,6)=1 if S ₁ ¹⁷(0, 1, 2, 4)=(F30, F198, F130, F98)E _(2,7)=1 if S ₁ ¹⁷(0, 1, 2, 4)=(F202, F184, F20, F213)E _(2,8)=1 if S ₁ ¹⁷(0, 1, 2, 4)=(F226, F45, F42, F178)E _(2,9)=1 if S ₁ ¹⁷(0, 1, 2, 4)=(F160, F135, F223, F142)E _(2,10)=1 if S ₁ ¹⁷(0, 1, 2, 4)=(F58, F21, F182, F148)E _(2,11)=1 if S ₁ ¹⁷(0, 1, 2, 4)=(F209, F145, F74, F215)E _(2,12)=1 if S ₁ ¹⁷(0, 1, 2, 4)=(F210, F52, F1, F247)E _(2,13)=1 if S ₁ ¹⁷(0, 1, 2, 4)=(F162, F240, F177, F190)E _(2,14)=1 if S ₁ ¹⁷(0, 1, 2, 4)=(F86, F96, F234, F143)E _(2,16)=1 if S ₁ ¹⁷(0, 1, 2, 4)=(F131, F204, F89, F40)E _(2,17)=1 if S ₁ ¹⁷(0, 1, 2, 4)=(F69, F50, F71, F108).

Syndrome decoder 600 combines the outputs of single error location logic610 and double error location logic 620 to generate an error locator bitE_(i) for each bit i, where 0≦i≦17, in accordance with steps 2 and 3 ofalgorithm A. To accomplish this, a gate array 631 responsive to logic630 produces a output of one whenever S₁ ¹⁷=1, that is, if S₁ ¹⁷(0, 1,2, 4)=(1, 0, 0, 0). Also, an OR gate 641 produces a zero whenever S₁=0,that is, whenever the first eight bits of the syndrome vector S are allzero.

For i=15, in step 2 of the algorithm, if S₁=0 and sp=1, then both inputsto AND gate 633 are one, causing OR gate 642 to output a one to generatean E₁₅ locator bit. Similarly, if S₁ ¹⁷=1 and sp=0, then both inputs toAND gate 635 are one, against causing OR gate 642 to output a one togenerate an E₁₅ locator bit. In the first instance, the E₁₅ locator bitindicates a single error at bit location 15, while in the second, theE₁₅ locator bit indicates a double error involving bit 15 and one otherbit location (as indicated by another E_(i)).

For 0≦i≦17 and i≠15, in step 3 of the algorithm, if S=column i of thefirst 8 rows of H₁ and S₁ ¹⁷=1, then logic 610 (E_(1,i))and logic 631input ones to the AND gate 632 for the particular i, causing the OR gate643 for the particular i to generate an E_(i) locator bit, this time fora single error at bit location i. Similarly, if the field element xi ofcolumn i of the first 8 rows of H₁ satisfies the equation x_(i)¹⁶S+x_(i)S₁ ¹⁶=S₁ ¹⁷, then logic 620 (E_(2,i)) and AND gate 634 inputones to the AND gate 636 for the particular i, again causing the OR gate643 for the particular i to generate an E_(i) locator bit, this time fora double error at bit location i and one other location (as indicated byanother E_(i)).

FIG. 8 shows uncorrectable error (UE) detection logic 660 for generatingthe uncorrectable error (UE) signal (FIG. 4). UE detection logic 660 isa part of syndrome decoder 600. Each of the AND blocks 661, 662, and 663outputs the logical AND of its inputs and each of the OR blocks 664outputs the logical OR of its inputs. NOR 665 outputs the inverse of thelogical OR of the inputs E_(2,i) from the output of logic 620.

UE detection logic 660 implements in hardware step 4 of Algorithm A.Thus, if (1) S₁ ¹⁷≠1, (2) S₁≠0 and (3) sp=1, then (1) circuit 631outputs a zero to inverter 651, causing that inverter to supply a firstone to AND gate 661, (2) OR gate 641 supplies a second one to AND gate661, causing that gate to supply a first one to AND gate 662, and (3)the sp line supplies a second one to AND gate 662; all of this causesAND gate 662 to input a one to OR gate 664, resulting in a one on the UEline. Alternatively, if (1) S₁ ¹⁷≠1, (2) sp=0 and (3) there is nosolution to the equation x_(i) ¹⁶S₁+x_(i)S₁ ¹⁶=S₁ ¹⁷, then (1) circuit631 outputs a zero to inverter 651, causing that inverter to supply afirst one to AND gate 663, (2) the sp line supplies a zero to inverter652, causing that inverter to supply a second one to AND gate 663, and(3) logic 620 supplies all zeros to NOR gate 665, causing that gate tooutput a third one to AND gate 663; all of this causes AND gate 663 toinput a one to OR gate 664, likewise resulting in a one on the UE line.

If (as shown in FIG. 4) errors in the check bits (7-15) are notcorrected, the associated error locators need not be generated for thispurpose. In such case, the circuits in single error location logic 610for generating E_(1,i) for 7≦i≦14, as well as the circuits forgenerating E₁₅, may be omitted. On the other hand, since step 4 ofAlgorithm A involves all 17 E_(2,i) values (0≦i≦17, i≠15), it is stillnecessary for double error location logic 620 to generate all of theseE_(2,i) values for UE detection logic 660 to fully implement this stepof the algorithm. If the E_(2,i) values for 7≦i≦14 are not generated inlogic 620, then the UE detection is reduced to determining whetherS¹⁷≠1, S≠0 and sp=1. The decoder 300 still provides double errorcorrecting and triple error detecting ability. However, it does notdetect as many errors beyond triple errors as the full decoder. Notealso that if logic 620 does generate E_(2,i) values for 7≦i≦14, thenumber of Fi XOR functions is reduced from 68 to 36. Thus, the overallsyndrome decoding circuitry would be reduced nearly by half, but at theexpense of reducing the probability of detecting four or more errors.

The capabilities of the present invention can be implemented insoftware, firmware, hardware or some combination thereof.

As one example, one or more aspects of the present invention can beincluded in an article of manufacture (e.g., one or more computerprogram products) having, for instance, computer usable media. The mediahas embodied therein, for instance, computer readable program code meansfor providing and facilitating the capabilities of the presentinvention. The article of manufacture can be included as a part of acomputer system or sold separately.

Additionally, at least one program storage device readable by a machine,tangibly embodying at least one program of instructions executable bythe machine to perform the capabilities of the present invention can beprovided.

The flow diagrams depicted herein are just examples. There may be manyvariations to these diagrams or the steps (or operations) describedtherein without departing from the spirit of the invention. Forinstance, the steps may be performed in a differing order, or steps maybe added, deleted or modified. All of these variations are considered apart of the claimed invention.

While the preferred embodiment to the invention has been described, itwill be understood that those skilled in the art, both now and in thefuture, may make various improvements and enhancements which fall withinthe scope of the claims which follow. These claims should be construedto maintain the proper protection for the invention first described.

1. A machine-implemented method for generating a code word from a dataword in accordance with an (18, 9) DEC-TED code, comprising the stepsof: receiving a 9-bit data word representing data to be encoded; andgenerating an 18-bit code word from the data word in accordance with alinear code defined by the following parity check matrix:${\underset{1}{\beta}}^{3\mspace{11mu}}\mspace{11mu}{\underset{1}{\beta}}^{6}\mspace{14mu}{\underset{1}{\beta}}^{12}\;{{\underset{1}{\beta}}^{7}\;}^{\;}\;{\underset{1}{\beta}}^{14}\mspace{11mu}{\underset{1}{\beta}}^{11}\mspace{11mu}{\underset{1}{\beta}}^{5}\mspace{14mu}{\underset{1}{\beta}}^{1}\mspace{14mu}{\underset{1}{\beta}}^{2}\mspace{14mu}{\underset{1}{\beta}}^{4}\mspace{14mu}{\underset{1}{\beta}}^{8}\mspace{11mu}{\underset{1}{\;\beta}}^{16}\mspace{11mu}{\underset{1}{\beta}}^{15}\mspace{14mu}{\underset{1}{\beta}}^{13}\mspace{14mu}{\underset{1}{\beta}}^{9}\mspace{14mu}\underset{\; 1}{\; 0}\mspace{25mu}{\underset{1}{\beta}}^{10}\mspace{11mu}\underset{1,}{1}$where β is a root of the polynomial x¹⁷−1 in the finite field of 256elements.
 2. The method of claim 1 in which β=α¹⁵ and α is a root of thebinary polynomial x⁸+x⁷+x⁶+x+1.
 3. A program storage device readable bya machine, tangibly embodying a program of instructions executable bythe machine to perform the method steps of claim
 1. 4. A method forgenerating a code word from a data word in accordance with an (18, 9)DEC-TED code, comprising the steps of: receiving a 9-bit data wordrepresenting data to be encoded; and generating an 18-bit code wordC=(c₀, c₁, . . . , c₁₇) from the data word in accordance with a linearcode in which bits c₀-c₆ and c₁₆-c₁₇ are data bits and bits c₇-c₁₅ areparity check bits satisfying the parity check equationCH₂ ^(t)=0, where H₂ ^(t) is the transpose of the parity check matrixH₂: $\begin{matrix}0 & 1 & 0 & 1 & 1 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 1 \\1 & 0 & 1 & 0 & 1 & 1 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 \\0 & 1 & 0 & 1 & 0 & 1 & 1 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 \\0 & 0 & 1 & 0 & 1 & 0 & 1 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 1 & 1 \\1 & 0 & 0 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 1 & 1 \\1 & 1 & 0 & 0 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 1 \\0 & 1 & 1 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 1 & 1 \\1 & 0 & 1 & 1 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 1 \\1 & 1 & 1 & 1 & 1 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 1.\end{matrix}$
 5. The method of claim 4, further comprising the steps of:receiving an 18-bit word R=(r₀, r₁, . . . , r₁₇) representing the sum ofthe code word C and an 18-bit error word E=(e₀, e₁, . . . , e₁₇); andgenerating a 9-bit syndrome vector S=(s₀, s₁, . . . s₈) from thereceived word R in accordance with the matrix equationS=RH₁ ^(t), where H₁ ^(t) is the transpose of the parity check matrixH₁: $\begin{matrix}\begin{matrix}0 & 0 & 1 & 1 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 1 & 1 & 1 & 0 & 0 & 0 & 1\end{matrix} \\\begin{matrix}0 & 0 & 0 & 0 & 1 & 1 & 1 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0\end{matrix} \\\begin{matrix}1 & 1 & 1 & 0 & 0 & 1 & 0 & 1 & 1 & 0 & 1 & 1 & 1 & 1 & 0 & 0 & 0 & 0\end{matrix} \\\begin{matrix}0 & 0 & 1 & 0 & 1 & 0 & 0 & 1 & 0 & 1 & 0 & 1 & 0 & 0 & 1 & 0 & 0 & 0\end{matrix} \\\begin{matrix}1 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 1 & 1 & 0 & 0 & 0\end{matrix} \\\begin{matrix}0 & 1 & 1 & 0 & 0 & 0 & 1 & 1 & 0 & 0 & 0 & 1 & 1 & 1 & 0 & 0 & 1 & 0\end{matrix} \\\begin{matrix}0 & 0 & 1 & 1 & 0 & 0 & 1 & 1 & 1 & 0 & 1 & 1 & 1 & 0 & 1 & 0 & 1 & 0\end{matrix} \\\begin{matrix}1 & 1 & 1 & 1 & 0 & 1 & 0 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0\end{matrix} \\\begin{matrix}0 & 0 & 1 & 0 & 1 & 0 & 1 & 1 & 0 & 1 & 1 & 1 & 0 & 1 & 0 & 1 & {1\;} & {0,}\end{matrix}\end{matrix}$ and; analyzing the received word R for errors using thesyndrome vector S.
 6. A program storage device readable by a machine,tangibly embodying a program of instructions executable by the machineto perform the method steps of claim
 4. 7. A method for decoding a codeword generated from a data word in accordance with an (18, 9) DEC-TEDcode, comprising the steps of: receiving an 18-bit word R=(r₀, r₁, . . ., r₁₇) representing the sum of an 18-bit code word C=(c₀, c₁, . . . ,c₁₇) encoding a 9-bit message and an 18-bit error word E=(e₀, e₁, . . ., e₁₇); and generating a 9-bit syndrome vector S=(s₀, s₁, . . . s₈) fromthe received word R in accordance with the matrix equationS=RH₁ ^(t), where H₁ ^(t) is the transpose of the matrix H₁:$\begin{matrix}\begin{matrix}0 & 0 & 1 & 1 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 1 & 1 & 1 & 0 & 0 & 0 & 1\end{matrix} \\\begin{matrix}0 & 0 & 0 & 0 & 1 & 1 & 1 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0\end{matrix} \\\begin{matrix}1 & 1 & 1 & 0 & 0 & 1 & 0 & 1 & 1 & 0 & 1 & 1 & 1 & 1 & 0 & 0 & 0 & 0\end{matrix} \\\begin{matrix}0 & 0 & 1 & 0 & 1 & 0 & 0 & 1 & 0 & 1 & 0 & 1 & 0 & 0 & 1 & 0 & 0 & 0\end{matrix} \\\begin{matrix}1 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 1 & 1 & 0 & 0 & 0\end{matrix} \\\begin{matrix}0 & 1 & 1 & 0 & 0 & 0 & 1 & 1 & 0 & 0 & 0 & 1 & 1 & 1 & 0 & 0 & 1 & 0\end{matrix} \\\begin{matrix}0 & 0 & 1 & 1 & 0 & 0 & 1 & 1 & 1 & 0 & 1 & 1 & 1 & 0 & 1 & 0 & 1 & 0\end{matrix} \\\begin{matrix}1 & 1 & 1 & 1 & 0 & 1 & 0 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0\end{matrix} \\\begin{matrix}0 & 0 & 1 & 0 & 1 & 0 & 1 & 1 & 0 & 1 & 1 & 1 & 0 & 1 & 0 & 1 & {1\;} & {0,}\end{matrix}\end{matrix}$ and; analyzing the received word R for errors using thesyndrome vector S.
 8. The method of claim 7 in which the analyzing stepcomprises the steps of: comparing bits of the syndrome vector S withcorresponding bits in one or more columns of the matrix H₁, andgenerating an indication of a single error in bit i of the code wordupon a successful comparison of the bits of the syndrome vector and theith column of the matrix H₁.
 9. The method of claim 8 in which bits 0-8of the syndrome vector S are compared with corresponding bits in one ormore columns of the matrix H₁.
 10. The method of claim 8 in which bits0-8 of the syndrome vector S are compared with corresponding bits incolumns 0-6 and 16-17 of the matrix H₁.
 11. The method of claim 8 inwhich bits 0-8 of the syndrome vector S are compared with correspondingbits in columns 0-14 and 16-17 of the matrix H₁.
 12. The method of claim7 in which the analyzing step comprises the step of: generating anindication of a double error involving bit i of the code word if thefield element x_(i) of column i of the first 8 rows of H₁ satisfies theequation x_(i) ¹⁶S+x_(i)S₁ ¹⁶=S₁ ¹⁷.
 13. The method of claim 7 in whichthe analyzing step comprising the steps of: generating an indication ofan error in bit 15 of the code word if S₁ is zero and sp is one, or ifS₁ ¹⁷ is one and sp is zero, where S₁ is the first 8 bits of thesyndrome vector S considered as a field element and sp is the exclusiveOR sum of the bits of the syndrome vector S.
 14. The method of claim 7in which the analyzing step comprises the step of: generating anindication of an error in bit i of the code word if S₁=column i of thefirst 8 rows of H₁ and S₁ ¹⁷ is one, or if the field element x_(i) ofcolumn i of the first 8 rows of H₁ satisfies the equation x_(i)¹⁶S+x_(i)S₁ ¹⁶=S₁ ¹⁷, S₁ ¹⁷ is not one, S₁ is not zero, and sp is zero,where S₁ is the first 8 bits of the syndrome vector S considered as afield element and sp is the exclusive OR sum of the bits of the syndromevector S.
 15. The method of claim 7 in which the analyzing stepcomprises the steps of: generating an indication of an uncorrectableerror in the code word if S₁ ¹⁷ is not one, S₁ is not zero and sp=1, orif S₁ ¹⁷ is not one, sp is zero and there is no solution to the equationx_(i) ¹⁶S₁+x_(i)S₁ ¹⁶=S₁ ¹⁷, where S₁ is the first 8 bits of thesyndrome vector S considered as a field element and sp is the exclusiveOR sum of the bits of the syndrome vector S.
 16. The method of claim 7in which the analyzing step comprises the step of: generating a valuerepresenting S₁ ¹⁷, where S₁ is the first 8 bits of the syndrome vectorS considered as a field element.
 17. The method of claim 16 in which thestep of generating a value representing S₁ ¹⁷ comprises the steps of:generating a value S₁ ¹⁷(0) as an XOR sum of S(0), S(2), S(3), S(6),S(0)S(1), S(0)S(5), S(0)S(7), S(1)S(2), S(1)S(6), S(1)S(7), S(2)S(4),S(2)S(6), S(3)S(6), S(3)S(7), S(4)S(5), S(4)S(7), where S(i) is bit i ofthe syndrome vector S and S(i)S(j) represents the product of S(i) andS(j); generating a value S₁ ¹⁷(1) as an XOR sum of S(1), S(3), S(4),S(7), S(0)S(2), S(0)S(3), S(0)S(6), S(1)S(2), S(1)S(6), S(2)S(3),S(2)S(7), S(3)S(5), S(3)S(7), S(4)S(7), S(5)S(6); generating a value S₁¹⁷(2) as an XOR sum of S(1), S(2), S(5), S(0)S(1), S(0)S(5), S(0)S(6),S(0)S(7), S(1)S(3), S(1)S(5), S(2)S(5), S(2)S(6), S(3)S(4), S(3)S(6),S(3)S(7), S(4)S(7), S(5)S(7); and generating a value S₁ ¹⁷(4) as an XORsum of S(1), S(2), S(3), S(4), S(6), S(0)S(1), S(0)S(2), S(0)S(4),S(0)S(5), S(1)S(2), S(1)S(4), S(1)S(5), S(1)S(6), S(2)S(3), S(2)S(4),S(2)S(5), S(2)S(7), S(4)S(5), S(4)S(6), S(5)S(7), S(6)S(7).
 18. Themethod of claim 17 in which the analyzing step further comprises thesteps of: generating values Fi, where each Fi is the XOR sum of the bitsof the syndrome vector S corresponding to the binary representation ofi, and i is 3, 4, 14, 18, 23, 26, 29, 30, 40, 44, 49, 50, 69, 71, 85,89, 98, 107, 108, 123, 130, 131, 137, 139, 168, 180, 183, 192, 198, 199,203, 204, 206, 232, 237, and 251; generating an indication of a doubleerror involving bit 0 of the code word if S₁₇(0, 1, 2, 4)=(F183, F232,F139, F29), where S₁₇(0, 1, 2, 4) is a vector having the respectivecomponents S₁₇(0), S₁₇(1), S₁₇(2), and S₁₇(4); generating an indicationof a double error involving bit 1 of the code word if S₁₇(0, 1, 2,4)=(F26, F251, F123, F18); generating an indication of a double errorinvolving bit 2 of the code word if S₁₇(0, 1, 2, 4)=(F44, F168, F199,F23); generating an indication of a double error involving bit 3 of thecode word if S₁₇(0, 1, 2, 4)=(F237, F206, F107, F3); generating anindication of a double error involving bit 4 of the code word if S₁₇(0,1, 2, 4)=(F192, F180, F137, F4); generating an indication of a doubleerror involving bit 5 of the code word if S₁₇(0, 1, 2, 4)=(F49, F203,F14, F85); generating an indication of a double error involving bit 6 ofthe code word if S₁₇(0, 1, 2, 4)=(F30, F198, F130, F98); generating anindication of a double error involving bit 16 of the code word if S₁₇(0,1, 2, 4)=(F131, F204, F89, F40); and generating an indication of adouble error involving bit 17 of the code word if S₁₇(0, 1, 2, 4)=(F69,F50, F71, F108).
 19. The method of claim 18 in which the analyzing stepfurther comprises the steps of: generating values Fi, where each Fi isthe XOR sum of the bits of the syndrome vector S corresponding to thebinary representation of i, and i is 1, 20, 21, 42, 45, 52, 58, 74, 86,96, 135, 142, 143, 145, 148, 160, 162, 177, 178, 182, 184, 190, 202,209, 210, 213, 215, 223, 226, 234, 240, and 247; generating anindication of a double error involving bit 7 of the code word if S₁₇(0,1, 2, 4)=(F202, F184, F20, F213); generating an indication of a doubleerror involving bit 8 of the code word if S₁₇(0, 1, 2, 4)=(F226, F45,F42, F178); generating an indication of a double error involving bit 9of the code word if S₁₇(0, 1, 2, 4)=(F160, F135, F223, F142); generatingan indication of a double error involving bit 10 of the code word ifS₁₇(0, 1, 2, 4)=(F58, F21, F182, F148); generating an indication of adouble error involving bit 11 of the code word if S₁₇(0, 1, 2, 4)=(F209,F145, F74, F215); generating an indication of a double error involvingbit 12 of the code word if S₁₇(0, 1, 2, 4)=(F210, F52, F1, F247);generating an indication of a double error involving bit 13 of the codeword if S₁₇(0, 1, 2, 4)=(F162, F240, F177, F190); and generating anindication of a double error involving bit 14 of the code word if S₁₇(0,1, 2, 4)=(F86, F96, F234, F143).
 20. A program storage device readableby a machine, tangibly embodying a program of instructions executable bythe machine to perform the method steps of claim
 7. 21. Apparatus forgenerating a code word from a data word in accordance with an (18, 9)DEC-TED code, comprising: an encoder for receiving a 9-bit data wordrepresenting data to be encoded and for generating an 18-bit code wordfrom the data word in accordance with a linear code defined by thefollowing parity check matrix:${\underset{1}{\beta}}^{3\mspace{11mu}}\mspace{11mu}{\underset{1}{\beta}}^{6}\mspace{14mu}{\underset{1}{\beta}}^{12}\;{{\underset{1}{\beta}}^{7}\;}^{\;}\;{\underset{1}{\beta}}^{14}\mspace{11mu}{\underset{1}{\beta}}^{11}\mspace{11mu}{\underset{1}{\beta}}^{5}\mspace{14mu}{\underset{1}{\beta}}^{1}\mspace{14mu}{\underset{1}{\beta}}^{2}\mspace{14mu}{\underset{1}{\beta}}^{4}\mspace{14mu}{\underset{1}{\beta}}^{8}\mspace{11mu}{\underset{1}{\;\beta}}^{16}\mspace{11mu}{\underset{1}{\beta}}^{15}\mspace{14mu}{\underset{1}{\beta}}^{13}\mspace{14mu}{\underset{1}{\beta}}^{9}\mspace{14mu}\underset{\; 1}{\; 0}\mspace{25mu}{\underset{1}{\beta}}^{10}\mspace{11mu}\underset{1,}{1}$where β is a root of the polynomial x¹⁷−1 in the finite field of 256elements.
 22. The apparatus of claim 21 in which β=α¹⁵ and α is a rootof the binary polynomial x⁸+x⁷+x⁶+x+1.
 23. Apparatus for generating acode word from a data word in accordance with an (18, 9) DEC-TED code,comprising: encoder for receiving a 9-bit data word representing data tobe encoded and for generating an 18-bit code word C=(c₀, c₁, . . . ,c₁₇) from the data word in accordance with a linear code in which bitsc₀-c₆ and c₁₆-c₁₇ are data bits and bits c₇-c₁₅ are parity check bitssatisfying the parity check equationCH₂ ^(t)=0, where H₂ ^(t) is the transpose of the parity check matrixH₂: $\begin{matrix}0 & 1 & 0 & 1 & 1 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 1 \\1 & 0 & 1 & 0 & 1 & 1 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 \\0 & 1 & 0 & 1 & 0 & 1 & 1 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 \\0 & 0 & 1 & 0 & 1 & 0 & 1 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 1 & 1 \\1 & 0 & 0 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 1 & 1 \\1 & 1 & 0 & 0 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 1 \\0 & 1 & 1 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 1 & 1 \\1 & 0 & 1 & 1 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 1 \\1 & 1 & 1 & 1 & 1 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 1.\end{matrix}$
 24. The apparatus of claim 23, further comprising: asyndrome generator for receiving an 18-bit word R=(r₀, r₁, . . . , r₁₇)representing the sum of the code word C and an 18-bit error word E=(e₀,e₁, . . . , e₁₇) and generating a 9-bit syndrome vector S=(s₀, s₁, . . .s₈) from the received word R in accordance with the matrix equationS=RH₁ ^(t), where H₁ ^(t) is the transpose of the parity check matrixH₁: $\begin{matrix}\begin{matrix}0 & 0 & 1 & 1 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 1 & 1 & 1 & 0 & 0 & 0 & 1\end{matrix} \\\begin{matrix}0 & 0 & 0 & 0 & 1 & 1 & 1 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0\end{matrix} \\\begin{matrix}1 & 1 & 1 & 0 & 0 & 1 & 0 & 1 & 1 & 0 & 1 & 1 & 1 & 1 & 0 & 0 & 0 & 0\end{matrix} \\\begin{matrix}0 & 0 & 1 & 0 & 1 & 0 & 0 & 1 & 0 & 1 & 0 & 1 & 0 & 0 & 1 & 0 & 0 & 0\end{matrix} \\\begin{matrix}1 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 1 & 1 & 0 & 0 & 0\end{matrix} \\\begin{matrix}0 & 1 & 1 & 0 & 0 & 0 & 1 & 1 & 0 & 0 & 0 & 1 & 1 & 1 & 0 & 0 & 1 & 0\end{matrix} \\\begin{matrix}0 & 0 & 1 & 1 & 0 & 0 & 1 & 1 & 1 & 0 & 1 & 1 & 1 & 0 & 1 & 0 & 1 & 0\end{matrix} \\\begin{matrix}1 & 1 & 1 & 1 & 0 & 1 & 0 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0\end{matrix} \\\begin{matrix}0 & 0 & 1 & 0 & 1 & 0 & 1 & 1 & 0 & 1 & 1 & 1 & 0 & 1 & 0 & 1 & {1\;} & {0,}\end{matrix}\end{matrix}$ and; a syndrome decoder for analyzing the received word Rfor errors using the syndrome vector S.
 25. Apparatus for decoding acode word generated from a data word in accordance with an (18, 9)DEC-TED code, comprising the steps of: a syndrome generator forreceiving an 18-bit word R=(r₀, r₁, . . . , r₁₇) representing the sum ofan 18-bit code word C=(c₀, c₁, . . . c₁₇) encoding a 9-bit message andan 18-bit error word E=(e₀, e₁, . . . , e₁₇) and generating a 9-bitsyndrome vector S=(s₀, s₁, . . . s₈) from the received word R inaccordance with the matrix equationS=RH₁ ^(t), where H₁ ^(t) is the transpose of the matrix H₁:$\begin{matrix}\begin{matrix}0 & 0 & 1 & 1 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 1 & 1 & 1 & 0 & 0 & 0 & 1\end{matrix} \\\begin{matrix}0 & 0 & 0 & 0 & 1 & 1 & 1 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0\end{matrix} \\\begin{matrix}1 & 1 & 1 & 0 & 0 & 1 & 0 & 1 & 1 & 0 & 1 & 1 & 1 & 1 & 0 & 0 & 0 & 0\end{matrix} \\\begin{matrix}0 & 0 & 1 & 0 & 1 & 0 & 0 & 1 & 0 & 1 & 0 & 1 & 0 & 0 & 1 & 0 & 0 & 0\end{matrix} \\\begin{matrix}1 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 1 & 1 & 0 & 0 & 0\end{matrix} \\\begin{matrix}0 & 1 & 1 & 0 & 0 & 0 & 1 & 1 & 0 & 0 & 0 & 1 & 1 & 1 & 0 & 0 & 1 & 0\end{matrix} \\\begin{matrix}0 & 0 & 1 & 1 & 0 & 0 & 1 & 1 & 1 & 0 & 1 & 1 & 1 & 0 & 1 & 0 & 1 & 0\end{matrix} \\\begin{matrix}1 & 1 & 1 & 1 & 0 & 1 & 0 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0\end{matrix} \\\begin{matrix}0 & 0 & 1 & 0 & 1 & 0 & 1 & 1 & 0 & 1 & 1 & 1 & 0 & 1 & 0 & 1 & {1\;} & {0,}\end{matrix}\end{matrix}$ and; a syndrome decoder for analyzing the received word Rfor errors using the syndrome vector S.
 26. The apparatus of claim 25 inwhich the syndrome decoder comprises: single error location logic forcomparing bits of the syndrome vector S with corresponding bits in oneor more columns of the matrix H₁ and generating an indication of asingle error in bit i of the code word upon a successful comparison ofthe bits of the syndrome vector and the ith column of the matrix H₁. 27.The apparatus of claim 26 in which bits 0-8 of the syndrome vector S arecompared with corresponding bits in one or more columns of the matrixH₁.
 28. The apparatus of claim 26 in which bits 0-8 of the syndromevector S are compared with corresponding bits in columns 0-6 and 16-17of the matrix H₁.
 29. The apparatus of claim 26 in which bits 0-8 of thesyndrome vector S are compared with corresponding bits in columns 0-14and 16-17 of the matrix H₁.
 30. The apparatus of claim 25 in which thesyndrome decoder comprises: double error location logic for generatingan indication of a double error involving bit i of the code word if thefield element x_(i) of column i of the first 8 rows of H₁ satisfies theequation x_(i) ¹⁶S+x_(i)S₁ ¹⁶=S₁ ¹⁷.
 31. The apparatus of claim 25 inwhich the syndrome decoder comprises: error location logic forgenerating an indication of an error in bit 15 of the code word if S₁ iszero and sp is one, or if S₁ ¹⁷ is one and sp is zero, where S₁ is thefirst 8 bits of the syndrome vector S considered as a field element andsp is the exclusive OR sum of the bits of the syndrome vector S.
 32. Theapparatus of claim 25 in which the syndrome decoder generates anindication of an error in bit i of the code word if S₁=column i of thefirst 8 rows of H₁ and S₁ ¹⁷ is one, or if the field element x_(i) ofcolumn i of the first 8 rows of H₁ satisfies the equation x_(i)¹⁶S+x_(i)S₁ ¹⁶S₁ ¹⁷ is not one, S₁ is not zero, and sp is zero, where S₁is the first 8 bits of the syndrome vector S considered as a fieldelement and sp is the exclusive OR sum of the bits of the syndromevector S.
 33. The apparatus of claim 25 in which the syndrome decodercomprises: uncorrectable error detection logic for generating anindication of an uncorrectable error in the code word if S₁ ¹⁷ is notone, S₁ is not zero and sp=1, or if S₁ ¹⁷ is not one, sp is zero andthere is no solution to the equation x_(i) ¹⁶S₁+x_(i)S₁ ¹⁶=S₁ ¹⁷, whereS₁ is the first 8 bits of the syndrome vector S considered as a fieldelement and sp is the exclusive OR sum of the bits of the syndromevector S.
 34. The apparatus of claim 25 in which the syndrome decodercomprises: logic for generating a value representing S₁ ¹⁷, where S₁ isthe first 8 bits of the syndrome vector S considered as a field element.35. The apparatus of claim 34 in which the logic for generating a valuerepresenting S₁ ¹⁷: generates a value S₁ ¹⁷(0) as an XOR sum of S(0),S(2), S(3), S(6), S(0)S(1), S(0)S(5), S(0)S(7), S(1)S(2), S(1)S(6),S(1)S(7), S(2)S(4), S(2)S(6), S(3)S(6), S(3)S(7), S(4)S(5), S(4)S(7),where S(i) is bit i of the syndrome vector S and S(i)S(j) represents theproduct of S(i) and S(j); generates a value S₁ ¹⁷(1) as an XOR sum ofS(1), S(3), S(4), S(7), S(0)S(2), S(0)S(3), S(0)S(6), S(1)S(2),S(1)S(6), S(2)S(3), S(2)S(7), S(3)S(5), S(3)S(7), S(4)S(7), S(5)S(6);generates a value S₁ ¹⁷(2) as an XOR sum of S(1), S(2), S(5), S(0)S(1),S(0)S(5), S(0)S(6), S(0)S(7), S(1)S(3), S(1)S(5), S(2)S(5), S(2)S(6),S(3)S(4), S(3)S(6), S(3)S(7), S(4)S(7), S(5)S(7); and generates a valueS₁ ¹⁷(4) as an XOR sum of S(1), S(2), S(3), S(4), S(6), S(0)S(1),S(0)S(2), S(0)S(4), S(0)S(5), S(1)S(2), S(1)S(4), S(1)S(5), S(1)S(6),S(2)S(3), S(2)S(4), S(2)S(5), S(2)S(7), S(4)S(5), S(4)S(6), S(5)S(7),S(6)S(7).
 36. The apparatus of claim 34 in which the syndrome decoderfurther comprises double error location logic for: generating values Fi,where each Fi is the XOR sum of the bits of the syndrome vector Scorresponding to the binary representation of i, and i is 3, 4, 14, 18,23, 26, 29, 30, 40, 44, 49, 50, 69, 71, 85, 89, 98, 107, 108, 123, 130,131, 137, 139, 168, 180, 183, 192, 198, 199, 203, 204, 206, 232, 237,and 251; generating an indication of a double error involving bit 0 ofthe code word if S₁₇(0, 1, 2, 4)=(F183, F232, F139, F29), where S₁₇(0,1, 2, 4) is a vector having the respective components S₁₇(0), S₁₇(1),S₁₇(2), and S₁₇(4); generating an indication of a double error involvingbit 1 of the code word if S₁₇(0, 1, 2, 4)=(F26, F251, F123, F18);generating an indication of a double error involving bit 2 of the codeword if S₁₇(0, 1, 2, 4)=(F44, F168, F199, F23); generating an indicationof a double error involving bit 3 of the code word if S₁₇(0, 1, 2,4)=(F237, F206, F107, F3); generating an indication of a double errorinvolving bit 4 of the code word if S₁₇(0, 1, 2, 4)=(F192, F180, F137,F4); generating an indication of a double error involving bit 5 of thecode word if S₁₇(0, 1, 2, 4)=(F49, F203, F14, F85); generating anindication of a double error involving bit 6 of the code word if S₁₇(0,1, 2, 4)=(F30, F198, F130, F98); generating an indication of a doubleerror involving bit 16 of the code word if S₁₇(0, 1, 2, 4)=(F131, F204,F89, F40); and generating an indication of a double error involving bit17 of the code word if S₁₇(0, 1, 2, 4)=(F69, F50, F71, F108).
 37. Theapparatus of claim 36 in which the syndrome decoder further comprisesdouble error location logic for: generating values Fi, where each Fi isthe XOR sum of the bits of the syndrome vector S corresponding to thebinary representation of i, and i is 1, 20, 21, 42, 45, 52, 58, 74, 86,96, 135, 142, 143, 145, 148, 160, 162, 177, 178, 182, 184, 190, 202,209, 210, 213, 215, 223, 226, 234, 240, and 247; generating anindication of a double error involving bit 7 of the code word if S₁₇(0,1, 2, 4)=(F202, F184, F20, F213); generating an indication of a doubleerror involving bit 8 of the code word if S₁₇(0, 1, 2, 4)=(F226, F45,F42, F178); generating an indication of a double error involving bit 9of the code word if S₁₇(0, 1, 2, 4)=(F160, F135, F223, F142); generatingan indication of a double error involving bit 10 of the code word ifS₁₇(0, 1, 2, 4)=(F58, F21, F182, F148); generating an indication of adouble error involving bit 11 of the code word if S₁₇(0, 1, 2, 4)=(F209,F145, F74, F215); generating an indication of a double error involvingbit 12 of the code word if S₁₇(0, 1, 2, 4)=(F210, F52, F1, F247);generating an indication of a double error involving bit 13 of the codeword if S₁₇(0, 1, 2, 4)=(F162, F240, F177, F190); and generating anindication of a double error involving bit 14 of the code word if S₁₇(0,1, 2, 4)=(F86, F96, F234, F143).